深度报告-20240219-华安证券-半导体深度报告_先进封装加速迭代_迈向2.5D_3D封装_37页_9mb

2.5D/3D More-than-Moore Packaging Technology Report Summary

Introduction/Report Overview

The report focuses on 2.5D/3D packaging technologies as part of the More-than-Moore approach, essential for enhancing AI, HBM, and high-performance computing systems. It covers key techniques, market trends, and future projections.

Key Technologies

• Flip-Chip and Bumping: Advanced interconnect methods using bumping (e.g., micro bump, C4 bump) for high-speed data transfer and reliability.
• Fan-In/Fan-Out WLCSP: Wafer-level chip scale packages enabling reduced form factors and improved I/O density.
• Chiplet Design: Modular approach for integrating multiple dies, supporting AI and heterogenous computing.
• CoWoS (Chip on Wafer on Substrate): Dominant packaging for HBM (High Bandwidth Memory) in GPUs like Nvidia's H100 and AMD's MI300, with variants like CoWoS-S and CoWoS-7.
• SiP (System in Package): Combines multiple chips into a single package for applications like memory and sensor integration.

Market Trends and Growth

• Market Projections: 2.5D/3D market CAGR is 6.26% (2022-2026), with 3D packaging growing at 18%. AI-driven demand fuels growth in CoWoS and CHIPLET segments.
• Player Analysis: OSATs (56.28%) dominate packaging assembly, with increasing adoption of CoWoS and SiP in AI workloads.
• Adoption Drivers: AI, high-bandwidth memory, and SoC/integration needs drive uptake, with technologies like HBM supporting speeds from 32 GB/s to over 800 GB/s.
• Technical Highlights: TSV (Through Silicon Via) dimensions range from 10μm×100μm to 45×65mm for bumping and RDL; HBM I/O counts increase, enabling GB/s to Tb/s data rates.

Conclusions

More-than-Moore technologies, including Chiplet and advanced packaging, are critical for sustaining performance gains in AI and computing, with CoWoS and SiP leading in high-density applications. Market share dynamics favor OSATs, and growth is projected to accelerate with ongoing AI and memory demands.