2024-01-15-开放数据中心委员会-2023数据中心224G可插拔模块交换机方案研究报告_61页_5mb

Summary of ODCC-2023-03002: Data Center 224G Pluggable Module Switch Solution Report

Background

The report addresses the growing demand for high-bandwidth network infrastructure driven by AI computing, particularly large-scale AI models requiring massive data centers. It emphasizes that next-generation networks must support higher speed, capacity, performance, cost-efficiency, and energy savings. Key points include the projection of 2025-2027 network iteration to 800G/1.6T with 224G-PAM4 SERDES as a solution for 102Tbps chips, and the need for modular systems like 224G pluggable modules to meet AI demands unless CPO or NPO alternatives prove superior in specific applications.

Network and Chip Trends

Data center network switches rely heavily on chip advancements. For example, Broadcom's Tomahawk chip evolved from 3.2Tbps in 2014 to 51.2Tbps in 2022, with SERDES speeds increasing from 25Gbps to 112Gbps or potentially 224Gbps. This trend leads to larger chip sizes, higher power consumption (e.g., potential 4-6x energy increase for 16x performance gain), and challenges in packaging and cooling. Light interconnects (e.g., QSFP-DD, OSFP, OSFP-XD) show promise with technologies like LPO reducing optical module power consumption by up to 50%, but CPO schemes face issues with maintenance, cost, and open ecosystem adoption.

Interconnect Evolution

224G-PAM4 signaling introduces stringent signal integrity requirements. Electrical interconnect designs include traditional PCB, NCC, CPC, and Vertical I/O schemes to manage losses and reflections. PCB materials need advanced properties (low Df, optimized copper roughness) to achieve low insertion loss. Copper cables and optical modules adapt to high rates, with interfaces like OSFP and QSFP evolving for backward compatibility and performance.

224G System Feasibility

The feasibility of 224G pluggable switches involves addressing packaging, heat dissipation, and power delivery. Recommendations include hybrid cooling (air and cold plates), vertical I/O connections to reduce stub effects, and power-efficient designs with integrated modules and vertical power supply strategies. Challenges include high chip power (up to 1000W), PCB manufacturing complexity, and path for efficient signal routing.

Testing Methodologies

Testing for 224G interfaces requires sophisticated tools: electrical tests use high-bandwidth oscilloscopes and bit error rate testers to evaluate transmitter/receiver performance and reflection losses. Optical tests involve advanced optical sampling scopes and potentially longer channels for receiver sensitivity, with emphasis on reducing noise and improving compatibility with emerging standards.

Impact and Recommendations

The solution supports scalable AI infrastructure but requires collaborative industry efforts to advance standards, improve manufacturing, and ensure interoperability across open ecosystems.